Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel

摘要

A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.

主权项

1. A method for implementing synchronized memory activities of multiple memory devices being accessed in parallel, said method comprising:
providing a control function coupled to a memory core including a plurality of memory cells, said control function receiving a command, address input; said control function generating an internal status signal for predefined internal memory activities; providing a switch coupled to said control function for generating an output signal responsive to said generated internal status signal; monitoring said generated internal status signal and said output signal of at least one of the multiple memory devices; and generating a control signal responsive to the monitored signals, said control signal for adjusting an event period to synchronize memory activities of the memory devices.