| 摘要 |
A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides. |
| 主权项 |
1. A method of fabricating a semiconductor device comprising at least two memory cells, wherein the at least two memory cells have first and second memory cells, each containing six transistors, which are two access transistors, two drive transistors, and two load transistors, comprising:
forming a first poly-silicon wiring layer, a first part of which is structured as a gate of a first access transistor of the first memory cell, and a second part of which is structured as a gate of a second access transistor of the second memory cell; forming a second poly-silicon wiring layer, a first part of which is structured as a gate of a first drive transistor of the first memory cell, and a second part of which is structured as a gate of a first load transistor of the first memory cell; forming a third poly-silicon wiring layer, a first part of which is structured as a gate of a second load transistor of the first memory cell, and a second part of which is structured as a gate of a second drive transistor of the first memory cell; forming a fourth poly-silicon wiring layer, a first part of which is structured as a gate of a second access transistor of the first memory cell; forming a fifth poly-silicon wiring layer, a first part of which is structured as a gate of a first drive transistor of the second memory cell, and a second part of which is structured as a gate of a first load transistor of the second memory cell; forming a sixth poly-silicon wiring layer, a first part of which is structured as a gate of a second load transistor of the second memory cell, and a second part of which is structured as a gate of a second drive transistor of the second memory cell; forming a seventh poly-silicon wiring layer, a first part of which is structured as a gate of a second access transistor of the second memory cell, wherein steps of forming the first, second, third, fourth, fifth, sixth, and seventh poly-silicon wiring layers comprise:
setting all distances between the first poly-silicon wiring layer and the third poly-silicon wiring layer, between the second poly-silicon wiring layer and the fourth poly-silicon wiring layer, between the second poly-silicon wiring layer and the fifth poly-silicon wiring layer, between the first poly-silicon wiring layer and sixth poly-silicon wiring layer, and between the fifth poly-silicon wiring layer and seventh poly-silicon wiring layer to be a same distance;setting all lengths of the first, second, third, fifth, and sixth poly-silicon wiring layers to be a same length; andsetting all aspect ratios of the first, second, third, fifth, and sixth poly-silicon wiring layers to be more than 5. |
