发明名称 |
Latency control circuit and method of controlling latency |
摘要 |
A latency control circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a clock signal by a delay time varied according to any one of dual locking points, and generate a loop change signal according to a locking point change; a control unit configured to generate a latency control signal in response to a reset signal, a delay signal generated by delaying the reset signal by a first delay time, and the loop change signal; and a latency signal generation unit configured to adjust a latency of a command signal in response to the latency control signal and output a latency signal. |
申请公布号 |
US8909972(B2) |
申请公布日期 |
2014.12.09 |
申请号 |
US201113219620 |
申请日期 |
2011.08.27 |
申请人 |
SK Hynix Inc. |
发明人 |
Kim Kyung Hoon;Kim Hong Bae |
分类号 |
G06F1/00;H03L7/06 |
主分类号 |
G06F1/00 |
代理机构 |
William Park & Associates Patent Ltd. |
代理人 |
William Park & Associates Patent Ltd. |
主权项 |
1. A latency control circuit comprising:
a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a clock signal with a delay time varied according to one of dual locking points, and generates a loop change signal according to a locking point change between the dual locking points; a control unit configured to generate a latency control signal in response to a reset signal, a delay signal generated by delaying the reset signal by a first delay time, and the loop change signal; and a latency signal generation unit configured to adjust a latency of a command signal in response to the latency control signal and output a latency signal. |
地址 |
Gyeonggi-do KR |