发明名称 Information processing apparatus or information processing method which supplies a clock to an external device
摘要 If data received by the an information processing apparatus from an external device is delayed by one cycle or more with respect to a clock of the information processing apparatus, the information processing apparatus may require an additional process for adjusting a data latch timing.;Delay information indicating a relationship between a calibration pattern to be received and an amount of cycle delay is stored in advance. Thus, the time required for detecting an amount of cycle delay, which is equivalent to the amount by which a signal for controlling a data latch mechanism in the information processing apparatus to stop its operation is delayed, can be reduced.
申请公布号 US8909970(B2) 申请公布日期 2014.12.09
申请号 US201013518344 申请日期 2010.12.21
申请人 Canon Kabushiki Kaisha 发明人 Momoi Akiyoshi;Morishita Koichi
分类号 H04L7/00;H04L7/10;H04L7/033 主分类号 H04L7/00
代理机构 Canon USA Inc IP Division 代理人 Canon USA Inc IP Division
主权项 1. An information processing apparatus comprising: a supply unit configured to supply a clock to an external device; an instruction unit configured to instruct the external device to transmit a calibration pattern; a receiving unit configured to receive external device data including the calibration pattern that is output from the external device in synchronization with the clock; a control unit configured to control the supply unit to stop supply of the clock in accordance with gating information indicating at which timing the supply of the clock is to be stopped; a storage unit configured to hold delay information indicating a relationship between a calibration pattern to be received by the receiving unit and an amount of cycle delay; a detection unit configured to detect the amount of cycle delay by comparing with the delay information a calibration pattern received, while the control unit controls the supply of the clock, by the receiving unit; and a delay unit configured to delay a data latch timing of the receiving unit in accordance with the amount of cycle delay.
地址 Tokyo JP