Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution

摘要

Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.

主权项

1. An apparatus comprising:
a plurality of data cache units (DCUs) to store locally retired instructions of speculatively executed threads, wherein the DCUs include a version bit per line to classify an speculative update status of each line; a merging level cache (MLC) coupled to the DCUs to merge data from the lines of the DCUs, wherein the MLC includes a speculative bit per cache line to indicate that a cache line contains a speculative state and last version bits to indicate which core of a plurality of cores that made a last change to a chunk, wherein a chunk is a granularity at which memory disambiguation between two speculative threads is detectable; and a inter-core memory coherency module (ICMC) to globally retire instructions of the speculatively executed threads in the MLC.