Parasitic lateral PNP transistor and manufacturing method thereof

摘要

A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and a P-type doped polysilicon pseudo buried layer located under each of the shallow trench field oxide regions on the outer side of the active regions serves as a collector region. The transistor has a C-B-E-B-C structure which alters the current path in the base region to a straight line, which can improve the current amplification capacity of the transistor and thus leads to a significant improvement of its current gain and frequency characteristics, and is further capable of reducing the area and increasing current intensity of the transistor. A manufacturing method of the parasitic lateral PNP transistor is also disclosed.

主权项

1. A parasitic lateral PNP transistor, comprising:
a P-type substrate; three shallow trench field oxide regions formed in the substrate; an N-type implanted layer formed beneath a top surface of the substrate and surrounding the three shallow trench field oxide regions, the N-type implanted layer including two portions each located between two adjacent ones of the three shallow trench field oxide regions and serving as a base region of the parasitic lateral PNP transistor; two N-type polysilicon layers formed on the top surface of the substrate and contacting with the two portions of the N-type implanted layer; a polysilicon pseudo buried layer formed under a bottom of each of the shallow trench field oxide regions and including a P-type impurity; a P-type doped region, formed around each polysilicon pseudo buried layer; wherein each P-type doped region is surrounded by and contacting with the N-type implanted layer, wherein the polysilicon pseudo buried layer and the P-type doped region under a bottom of a middle one of the three shallow trench field oxide regions jointly serve as an emitter region of the parasitic lateral PNP transistor, and the polysilicon pseudo buried layer and the P-type doped region under a bottom of each of the shallow trench field oxide regions adjacent to the middle shallow trench field oxide region jointly serve as a collector region of the parasitic lateral PNP transistor.