发明名称 |
High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate |
摘要 |
Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors. |
申请公布号 |
US8910108(B2) |
申请公布日期 |
2014.12.09 |
申请号 |
US201414247078 |
申请日期 |
2014.04.07 |
申请人 |
Mentor Graphics Corporation |
发明人 |
Suaya Roberto |
分类号 |
G06F11/22;G06F17/50 |
主分类号 |
G06F11/22 |
代理机构 |
Klarquist Sparkman, LLP |
代理人 |
Klarquist Sparkman, LLP |
主权项 |
1. One or more computer-readable storage media storing computer-executable instructions which when executed by a computer cause the computer to perform a method, the method comprising:
receiving layout information indicative of at least signal-wire segments in a circuit design; identifying at least one signal-wire segment having a length that exceeds a transverse distance to a nearest neighboring return path by more than a threshold amount; performing a first impedance extraction technique for the identified at least one signal-wire segment, the first impedance extraction technique generating a first representation of impedance effects in the circuit design; and performing a second impedance extraction technique for other signal-wire segments in the circuit design, the second impedance extraction technique generating a second representation of the impedance effects in the circuit design, wherein the first impedance extraction technique and the second impedance extraction technique both account for electrical effects caused by a multi-layer substrate, and wherein the first impedance extraction technique is computationally more efficient but less accurate than the second impedance extraction technique. |
地址 |
Wilsonville OR US |