| 摘要 |
PROBLEM TO BE SOLVED: To provide a vertical channel junction SiC power JFET in which the interval between gate regions is controlled with high accuracy and the channel region, defined by the gate interval and the gate depth, is formed with a high aspect ratio by ensuring the gate depth, and to provide a method for manufacturing the same.SOLUTION: A floating gate region 5 is formed at a lower position spaced apart from a source region 6, between gate regions 4. |
