发明名称 |
A PULSE CLOCK GENERATION LOGIC WITH BUILT-IN LEVEL SHIFTER AND PROGRAMMABLE RISING EDGE AND PULSE WIDTH |
摘要 |
<p>Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.</p> |
申请公布号 |
KR20140139595(A) |
申请公布日期 |
2014.12.05 |
申请号 |
KR20147029964 |
申请日期 |
2013.03.28 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
GE SHAOPING;CHAI CHIAMING;LILES STEPHEN EDWARD;NGUYEN LAM V.;FISCHER JEFFREY HERBERT |
分类号 |
G06F1/04;G11C7/22;G11C11/419 |
主分类号 |
G06F1/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|