发明名称 |
INTEGRATED CIRCUIT |
摘要 |
An integrated circuit that does not involve increase in power consumption or decrease in switching probability that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period τ has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of information processing of the basic circuit element 1A satisfies the following relation:;τ>λ1/f1(0<λ1≦1). |
申请公布号 |
US2014355330(A1) |
申请公布日期 |
2014.12.04 |
申请号 |
US201214369974 |
申请日期 |
2012.12.04 |
申请人 |
TOHOKU UNIVERSITY |
发明人 |
Endoh Tetsuo;Ohsawa Takashi;Koike Hiroki;Hanyu Takahiro;Ohno Hideo |
分类号 |
G11C13/00 |
主分类号 |
G11C13/00 |
代理机构 |
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代理人 |
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主权项 |
1. An integrated circuit, comprising:
a memory element where write occurs when specified period τ has elapsed after a write signal is input; and a basic circuit including elementary devices that constitute a circuit and having a data retaining function, wherein an operation frequency f1 in a first operation mode in the process of information processing of the basic circuit satisfies the following relation:
τ>λ1/f1(0<λ1≦1) where, λ1 represents the ratio of time when write into the memory element is being performed in a cycle of the first operation mode (1/f1) in the process of information processing of the basic circuit. |
地址 |
Sendai-shi, Miyagi JP |