发明名称 PARALLEL CRC COMPUTATION WITH DATA ENABLES
摘要 Methods and devices generate cyclic redundancy check (CRC) values for a sequence of parallel words of data. The data words may have only some of the bits enabled. The input words are preconditioned, and then a common block generates a CRC remainder value. A specific preconditioning is selected based on the number of enabled bits. Additional post-processing may be performed to the CRC remainder.
申请公布号 US2014359404(A1) 申请公布日期 2014.12.04
申请号 US201314135437 申请日期 2013.12.19
申请人 Vitesse Semiconductor Corporation 发明人 Kumar K. Venkat Praveen;Chattar Nihit;Rajput Dishant Singh
分类号 H04L1/00;G06F11/10 主分类号 H04L1/00
代理机构 代理人
主权项
地址 Camarillo CA US