发明名称 Cache Memory Controller for Accelerated Data Transfer
摘要 A cache memory controller in a computer system, such as a multicore processing system, provides compression for writes to memory, such as an off-chip memory, and decompression after reads from memory. Application accelerator processors in the system generate application data and requests to read/write the data from/to memory. The cache memory controller uses information relating location parameters of buffers allocated for application data and sets parameters to configure compression and decompression operations. The cache memory controller monitors memory addresses specified in read requests and write requests from/to the first memory. The requested memory address is compared to the location parameters for the allocated buffers to select the set of parameters for the particular application data. Compression or decompression is applied to the application data in accordance with the selected set of parameters. The data size of the data transferred to/from memory is reduced.
申请公布号 US2014359219(A1) 申请公布日期 2014.12.04
申请号 US201313907745 申请日期 2013.05.31
申请人 Altera Corporation 发明人 EVANS ALLAN M.;WILLIAMS CURTIS M.
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项 1. A computer system, comprising: a central processing unit (CPU) responsive to instructions of a computer program; one or more application accelerator processors in communication with the CPU; and a cache memory controller in communication with the CPU, the application accelerator processor(s) and a first memory, the cache memory controller including an encoder to compress application data from the application accelerator processor(s) for writes to the first memory and a decoder to decompress compressed application data from reads of the first memory, wherein the CPU is responsive to instructions to allocate buffers in the first memory to store the application data provided by respective application accelerator processors and to provide location parameters representing sets of memory addresses allocated for the respective buffers to the cache memory controller, wherein the cache memory controller monitors memory addresses specified in respective read requests and write requests from/to the first memory.
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