DYNAMIC OPTIMIZATION OF PIPELINED SOFTWARE

摘要

In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.

主权项

1. A system comprising:
a processor including:
at least one core to execute operations of a loop;stage insertion logic to add a delay stage to the loop to increase a lifetime of a register associated with a first variable of the loop and to delay storage of contents of the register; and a dynamic random access memory (DRAM).