| 摘要 |
The present invention relates to a shift register, which can reduce power consumption, and a method for driving the same. The shift register comprises: a plurality of stages which sequentially output scan pulses using at least one start pulse and a plurality of clock pulses, wherein each stage includes: a node control unit to control voltages of a first node and a second node in response to a first carry signal of a front stage provided before at least a first stage and a second carry signal of a rear stage provided after at least the first stage; and an output buffer unit to output the scan pulses according to the voltage states of the first and second nodes. The node control unit precharges the first node of the rear stage provided after at least a second stage by connecting the first node provided in the corresponding stage to the first node of the rear stage provided after at least the second stage. |
