发明名称 Packaging of High Performance System Topology for NAND Memory Systems
摘要 A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package.
申请公布号 US2014355325(A1) 申请公布日期 2014.12.04
申请号 US201313904770 申请日期 2013.05.29
申请人 SanDisk Technologies Inc. 发明人 Tam Eugene Jinglun
分类号 G11C5/06 主分类号 G11C5/06
代理机构 代理人
主权项 1. A non-volatile memory integrated circuit, comprising: a plurality of external contact pads, including: a first set of a plurality of N external contact pads; anda second set of N external contact pads; a primary circuitry portion including a non-volatile memory array and associated peripheral circuitry and having, when operating in a first mode, N input lines and N output lines; and switching circuit connected to the first and second sets of external contact pads connected to the input and output lines, where the switching circuit can selectively attach the first and second sets of external contact pads to the input and output lines in either a first configuration, where the N input lines are attached to the first set of external contact pads and the N output lines are attached to the second set of external contact pads, or in a second configuration, where the N input lines are attached to the second set of external contact pads and the N output lines are attached to the first set of external contact pads.
地址 Plan TX US