LOCK DETECTOR FOR DIGITAL PHASE-LOCKED LOOP

摘要

A phase locked loop (PLL) lock detector may be configured to observe the phase error signal from a phase comparator of a PLL circuit. The PLL lock detector may accumulate a sum of phase errors and compare the sum of phase errors to determine whether the PLL circuit is locked in phase with the reference signal. Various modifications to the phase error signal and sum of phase errors may be used to improve the efficiency of the PLL lock detector. Configurable settings for the accumulator and a comparator may be used to adjust the operation of the PLL lock detector.

主权项

1. A phase-locked loop (PLL) circuit comprising:
a phase comparator configured to:
determine a first phase error between a reference signal and a feedback signal of the PLL circuit, anddetermine a second phase error between the reference signal and the feedback signal of the PLL circuit; and a PLL lock detector configured to:
determine a sum of the first phase error and the second error, anddetermine whether the sum is below a threshold value.