| 摘要 |
PROBLEM TO BE SOLVED: To provide a system and a method that are high-speed, low-cost, and low-power for detecting and reproducing data and a clock signal in a communication system.SOLUTION: A clock data recovery circuit (CDR) operates to reproduce data from a serial input signal. The CDR uses over-sampling to perform sampling of the serial input signal by a plurality of phases. The CDR generates the plurality of phases from a reference clock that is not locked to data transfer speed of the serial input signal. The CDR uses up to two phases at one time. |
