| 发明名称 |
MECHANISM FOR ISSUING REQUESTS TO AN ACCELERATOR FROM MULTIPLE THREADS |
| 摘要 |
An apparatus is described having multiple cores, each core having: a) a CPU; b) an accelerator; and, c) a controller and a plurality of order buffers coupled between the CPU and the accelerator. Each of the order buffers is dedicated to a different one of the CPU's threads. Each one of the order buffers is to hold one or more requests issued to the accelerator from its corresponding thread. The controller is to control issuance of the order buffers' respective requests to the accelerator. |
| 申请公布号 |
US2014359629(A1) |
申请公布日期 |
2014.12.04 |
| 申请号 |
US201213992865 |
申请日期 |
2012.03.30 |
| 申请人 |
Ronen Ronny;Ginzburg Boris;Weissmann Eliezer |
发明人 |
Ronen Ronny;Ginzburg Boris;Weissmann Eliezer |
| 分类号 |
G06F9/48;G06F12/10 |
主分类号 |
G06F9/48 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus, comprising:
multiple cores, each core having:
a) a CPU;b) an accelerator;c) a controller and a plurality of order buffers coupled between said CPU and said accelerator, each of said order buffers dedicated to a different one of said CPU's threads, each one of said order buffers to hold one or more requests issued to said accelerator from its corresponding thread, said controller to control issuance of said order buffers' respective requests to said accelerator. |
| 地址 |
Haifa IL |
