REDUCED POWER MODE OF A CACHE UNIT

摘要

In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a plurality of cores; and a cache unit reserved for a first core of the plurality of cores, the cache unit comprising a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode, wherein the first operating mode comprises use of both the first cache slice and the second cache slice, and wherein the second operating mode comprises use of the first cache slice and disabling the second cache slice.