SHIFT REGISTER CIRCUIT AND DRIVING METHOD THEREOF

摘要

An Nth shift register unit includes an input circuit, a voltage regulator, and an output circuit. The input circuit is disposed to control a voltage at a control node of the Nth shift register unit according to a first scan signal of an (N−K)th shift register unit or a second scan signal of an (N+K)th shift register unit. The voltage regulator includes a first coupling element coupled to a first clock, a first switch disposed to receive the voltage at the control node and generate a reverse bias for reducing current leakage, and a switch control unit disposed to control the first switch according to the first clock. The output circuit is disposed to output a third scan signal.

主权项

1. A shift register circuit comprising a plurality of shift register units, an Nth shift register unit of the shift register circuit comprising:
an input circuit configured to control a voltage at a control node of the Nth shift register unit according to a first scan signal of an (N−K)th shift register unit of the shift register circuit or a second scan signal of an (N+K)th shift register unit of the shift register circuit wherein N and K are positive integers, and N≧K; a voltage regulator comprising:
a first coupling element comprising a first terminal and a second terminal, the first terminal being configured to receive a first clock signal;a first switch comprising a first terminal electrically coupled to the second terminal of the first coupling element, a control terminal electrically coupled to the input circuit and configured to receive the voltage at the control node of the Nth shift register unit, and a second terminal; anda switch control unit electrically coupled to the second terminal of the first switch and a ground terminal and configured to control a voltage at the second terminal of the first switch according to the first clock signal and to generate a periodical reverse bias between the control terminal of the first switch and the second terminal of the first switch; and an output circuit comprising a first terminal configured to receive the first clock signal, a control terminal electrically coupled to the input circuit to receive the voltage at the control node of the Nth shift register unit, and a second terminal configured to output a third scan signal of the Nth shift register unit.