| 主权项 |
1. A system comprising:
a memory array including a way, the way including lower address memory cells for storing data and including higher address memory cells for storing data, the lower address memory cells having lower addresses compared to addresses of the higher address memory cells; a read and compare circuit coupled to the memory array, the read and compare circuit for performing a read operation, the read operation including reading the data stored within the lower address memory cells and for reading the data stored within the higher address memory cells, the read and compare circuit for comparing the data stored within the lower address memory cells with information received from a storage device to generate a result of comparison, the read and compare circuit for comparing the data stored within the higher address memory cells with the information to generate a result of comparison; and a merge and multiplex circuit coupled to the read and compare circuit, the merge and multiplex circuit for merging the result of comparison generated based on the comparison with the lower address memory cells and the result of comparison generated based on the comparison with the higher address memory cells to create a merged outcome of comparison, the merged outcome of comparison indicating whether the way has bits that match the information, the merge and multiplex circuit for selecting between providing the merged outcome of comparison during the read operation as an output and providing an indication of a selection of the way during a write operation as an output. |
