SEMICONDUCTOR LAYOUT STRUCTURE AND TESTING METHOD THEREOF

摘要

A semiconductor layout structure and a testing method thereof are disclosed. The semiconductor layout structure includes a device under test (DUT), a first testing pad, a second testing pad and a plurality of third testing pads. The DUT includes a plurality of metal-oxide-semiconductor (MOS) transistors. Each of the MOS transistors includes a first terminal, a second terminal and a third terminal. The first testing pad is coupled to the first terminals for being applied a first voltage. The second testing pad is coupled to the second terminals for being applied a second voltage. The third testing pads are respectively coupled to the third testing pads for being applied a third voltage. The third testing pads are electrical insulated from each other. The third voltage is larger than the first voltage and the second voltage.

主权项

1. A semiconductor layout structure, comprising:
a device under test (DUT) including a plurality of metal-oxide-semiconductor (MOS) transistors, each of the MOS transistors including a first terminal, a second terminal and a third terminal; a first testing pad, coupled to the first terminals for being applied a first voltage; a second testing pad, coupled to the second terminals for being applied a second voltage; and a plurality of third testing pads, respectively coupled to the third testing pads for being applied a third voltage, wherein the third testing pads are electrical insulated from each other, and the third voltage is larger than the first voltage and the second voltage.