Stress Compensation Layer to Improve Device Uniformity

摘要

The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices.

主权项

1. An integrated chip, comprising:
a stressed element located within a back-end-of-the-line stack disposed over a semiconductor substrate; a first stressing layer located over the stressed element and configured to induce a first stress upon the stressed element; and a first stress compensation layer located over the stressed element and configured to provide a first counter-stress configured to reduce the first stress on the stressed element.