发明名称 DRIVING METHOD OF SEMICONDUCTOR DEVICE
摘要 In a memory cell including first to third transistors, the potential of a bit line is set to VDD or GND when data is written through the first transistor. In a standby period, the potential of the bit line is set to GND. In reading operation, the bit line is brought into a floating state at GND, and a source line is set to a potential VDD−α, consequently, the third transistor is turned on. Then, the potential of the source line is output according to the potential of a gate of the second transistor. Note that α is set so that the second transistor is surely off even when the potential of the gate of the second transistor becomes lower from VDD by ΔV in the standby period. That is, Vth+ΔV<α is satisfied where Vth is the threshold value of the second transistor.
申请公布号 US2014355339(A1) 申请公布日期 2014.12.04
申请号 US201414288894 申请日期 2014.05.28
申请人 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. 发明人 Inoue Hiroki;Matsuzaki Takanori;Atsumi Tomoaki
分类号 G11C7/12;G11C7/06 主分类号 G11C7/12
代理机构 代理人
主权项 1. A driving method of a semiconductor device including a first word line, a second word line, a first bit line, a second bit line, a first wiring, a first transistor, a second transistor, and a third transistor between the second transistor and the second bit line or between the second transistor and the first wiring, wherein a gate of the first transistor is electrically connected to the first word line, one of a source and a drain of the first transistor is electrically connected to the first bit line, and the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein one of a source and a drain of the second transistor is electrically connected to the first wiring to which a potential V1 is supplied, and the other of the source and the drain of the second transistor is electrically connected to the second bit line, and wherein a gate of the third transistor is connected to the second word line, the method comprising the steps of: setting a potential of the first bit line to a potential VH or a potential VL that is lower than VH and turning on the first transistor; turning off the first transistor; and bringing the second bit line into a floating state at a potential V2, and then turning on the third transistor, wherein V2<V1<V3−Vth is satisfied where: Vth is a threshold value of the second transistor; and V3 is a potential of the gate of the second transistor after a retention period when the potential of the first bit line is set to VH, and wherein the retention period is a period between the step of turning off the first transistor and the step of bringing the second bit line into the floating state.
地址 Atsugi-shi JP