STRUCTURED PLACEMENT OF HIERARCHICAL SOFT BLOCKS DURING PHYSICAL SYNTHESIS OF AN INTEGRATED CIRCUIT

摘要

Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative placement information. A compiler receives a circuit description which includes an instance of an SSB and unfolds the instance according to the placement template to generate a modified circuit description which includes the relative placement information. The placement of circuit objects is optimized while maintaining relative locations for cells of the SSB instance according to the relative placement information. The SSB may be hierarchical. Gate resizing of cells in the SSB instance may result in a change in its bounds. A timing optimization procedure for the modified circuit description may be carried out while hiding internal details of the SSB instance. For example, buffers may be inserted in nets external to the SSB instance while preventing insertion of buffers in any internal nets.

主权项

1. A method for designing a layout of an integrated circuit comprising:
receiving a library file having at least one placement template for a structured soft block composed of a pre-defined set of cells with relative placement information for the pre-defined set of cells, by executing first instructions in a computer system; receiving a circuit description for the integrated circuit which includes a plurality of cells and at least one instance of the structured soft block interconnected to form a plurality of nets, by executing second instructions in the computer system; unfolding the structured soft block instance according to the placement template to generate a modified circuit description which includes the relative placement information for cells of the structured soft block instance, by executing third instructions in the computer system; optimizing a placement of the plurality of cells and the structured soft block instance while maintaining relative locations for cells of the structured soft block instance according to the relative placement information, by executing fourth instructions in the computer system; resizing one or more gates in at least one cell of the structured soft block instance such that physical bounds of the structured soft block instance change, by executing fifth instructions in the computer system; and carrying out a timing optimization procedure for the modified circuit description while maintaining the relative locations for cells of the structured soft block instance and preventing any changes to internal details of the structured soft block instance, by executing sixth instructions in the computer system, wherein the timing optimization procedure includes insertion of one or more buffers in at least one net external to the structured soft block instance but prevents insertion of any buffers in any net internal to the structured soft block instance.