IMPROVED COUPLING GATES STRAPPING OF SPLIT GATE ARRAY NON-VOLATILE FLOATING GATE MEMORY CELLS

摘要

The present invention an array of non-volatile memory cells has a semiconductor substrate of a first conductivity type with a top surface. A plurality of spaced apart first regions of a second conductivity type are in the substrate along the top surface. Each first region extends in a row direction. A plurality of spaced apart second regions of the second conductivity type are in the substrate along the top surface. Each second region is spaced apart from an associated first region in a column direction, perpendicular to the row direction. A channel region is defined between each second region and its associated first region in the column direction. Each channel region has a first portion and a second portion. A plurality of spaced apart word line gates extend in the row direction. Each word line gate is positioned over and is insulated from the first portion of a channel region.