发明名称 シリアルポートメモリ通信の待ち時間および信頼性を改善するための方法およびシステム
摘要 <p>A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.</p>
申请公布号 JP5635521(B2) 申请公布日期 2014.12.03
申请号 JP20110534681 申请日期 2009.10.27
申请人 发明人
分类号 G06F12/06;G06F12/00;G06F13/16 主分类号 G06F12/06
代理机构 代理人
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