Method for protecting a programmable cryptography circuit, and circuit protected by said method

摘要

A programmable cryptography circuit includes memory-based cells defining the logic function of each cell, integrating a differential network capable of carrying out calculations on pairs of binary variables, including a first network of cells implementing logic functions on the first component of the pairs and a second network of dual cells operating in complementary logic on the second component of the pair. A calculation step includes a precharge phase, in which the variables are put into a known state at the output of the cells, and an evaluation phase in which a calculation is made by the cells. A phase of synchronizing the variables is inserted before the evaluation phase or the precharge phase in each cell capable of receiving several signals conveying input variables, the synchronization being carried out on the most delayed signal.

主权项

1. A method for protecting a programmable cryptography circuit, said method comprising:
using gates comprising table-based cells defining the logic function of each of the table-based cells, the programmable cryptography circuit being configured to integrate a differential network configured to make calculations on binary variables, each of the binary variables comprising pairs of signals, the differential network comprising a first network of cells implementing logic functions on a first component of the pairs and of signals and a second network of dual cells operating in complementary logic on the second component of the pairs of signals, and making calculations on the binary variables during:
a precharge phase, in which the binary variables are put into a known state at an input of each cell of the differential network,an evaluation phase, in which a calculation is made by each cell of the differential network, anda synchronization phase, in which multiple signals representing multiple input binary variables are received and logic takes place on the multiple input binary variables, the synchronization phase being carried out before each of the precharge and evaluation phase, and the synchronization phase being carried out on a signal of the multiple signals having a greatest delay.