Dynamic random access memory device with improved control circuitry for the word lines

摘要

A dynamic random access memory device may include DRAM memory cells including several lines of memory cells, and line selection circuitry associated with each line. The line selection circuitry may include a first voltage-elevator stage configured to receive two initial control logic signals each having an initial voltage level corresponding to a first logic state, and to deliver two intermediate control logic signals each having an intermediate voltage level above the initial level and corresponding to the first logic state. The line selection circuitry may also include a control circuit to be supplied by PMOS transistors with a supply voltage having a second voltage level greater than the intermediate voltage level, and configured to, in the presence of the two intermediate control logic signals have their first logic state deliver to the gates of the memory cell transistors, a selection logic signal having the second voltage level.

主权项

1. A random access memory device comprising:
a plurality of dynamic random access memory (DRAM) cells, and line selection circuitry associated therewith and comprising
a first voltage-elevator stage configured to receive two initial control logic signals each having an initial voltage level corresponding to a first logic state and to deliver first and second intermediate control logic signals each having an intermediate voltage level above the initial voltage level and corresponding to the first logic state, anda control circuit comprising a first pair of PMOS transistors to be coupled with a supply voltage having a second voltage level greater than the intermediate level, said control circuit configured to, in the presence of the first and second intermediate control logic signals having their first logic state, deliver a selection logic signal having the second voltage level.