DELAY LINE TIME-TO-DIGITAL CONVERTER

摘要

The present invention provides a method of operating a time-to-digital converter when a delay line propagation time is shorter than an operation frequency period but is longer than half of the operation frequency period by using a latch operating at a phase opposite to phases of two delay lines in order to implement the time-digital converter. When a signal is input to the delay time, if the signal is propagated longer than half of the operation frequency period, a delay line to be used in interpolating less than the operation frequency period as compared with a case of propagating an end of the delay line is selected and used. The present invention may implement a time-to-digital converter in a logic circuit with a short delay line propagation time by attenuating limitation of an operation frequency.