Semiconductor chip layout

摘要

A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.

主权项

1. A semiconductor device comprising:
a first die comprising:
at least two IP cores on the first die, wherein at least one of the IP cores is disposed on each side of a centrally-located axis on the first die, anda serial interface positioned on the central region of the first die between said IP cores on the first die, wherein the serial interface includes a plurality of transmitter ports and a plurality of receiver ports.