| 发明名称 |
Microprocessor systems and methods for handling instructions with multiple dependencies |
| 摘要 |
A processor includes an instruction unit which provides instructions for execution by the processor, a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions, and a plurality of execution queues coupled to the decode/issue unit. Each issued instruction from the decode/issue unit is stored into an entry of at least one queue of the plurality of execution queues, wherein each entry of the plurality of execution queues is configured to store an issued instruction and a duplicate indicator corresponding to the issued instruction which indicates whether or not a duplicate instruction of the issued instruction is also stored in an entry of another queue of the plurality of execution queues. |
| 申请公布号 |
US8904150(B2) |
申请公布日期 |
2014.12.02 |
| 申请号 |
US201113116325 |
申请日期 |
2011.05.26 |
| 申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Tran Thang M.;Robinson Leick D. |
| 分类号 |
G06F15/00;G06F9/30;G06F9/40 |
主分类号 |
G06F15/00 |
| 代理机构 |
|
代理人 |
Bertani Mary Jo;Chiu Joanna G. |
| 主权项 |
1. A processor, comprising:
an instruction unit which provides instructions for execution by the processor; a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions; a plurality of execution queues coupled to the decode/issue unit, wherein each issued instruction from the decode/issue unit is stored into an entry of at least one queue of the plurality of execution queues, and wherein each entry of the plurality of execution queues is configured to store an issued instruction and a duplicate indicator corresponding to the issued instruction which indicates whether or not a duplicate instruction of the issued instruction is also stored in an entry of another queue of the plurality of execution queues. |
| 地址 |
Austin TX US |
