Shared-bit-line bit line setup scheme

摘要

Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings, wherein each pair of the one or more pairs of NAND strings shares a common bit line. In some embodiments, a pair of NAND strings includes an odd NAND string adjacent to an even NAND string. Prior to programming a memory cell associated with the even NAND string, an odd channel associated with the odd NAND string (i.e., the NAND string of the pair that is not selected for programming) is precharged to a bit line inhibit voltage, floated, and then boosted to a second voltage greater than the bit line inhibit voltage as an even channel associated with the even NAND string is precharged. Subsequently, the odd channel may be boosted (e.g., via self-boosting) prior to programming the memory cell.

主权项

1. A non-volatile storage system, comprising:
a first NAND string in communication with a shared bit line, the first NAND string includes a first channel; a second NAND string in communication with the shared bit line, the second NAND string includes a second channel; and one or more managing circuits in communication with the first NAND string and the second NAND string, the one or more managing circuits precharge the first channel to a first voltage at a first point in time, the precharging of the first channel boosts the second channel to a first boosted voltage less than the first voltage, the one or more managing circuits precharge the second channel to the first voltage at a second point in time subsequent to the first point in time, the precharging of the second channel boosts the first channel to a second voltage greater than the first voltage, the one or more managing circuits set the shared bit line to a programming voltage at a third point in time subsequent to the second point in time.