N-channel and P-channel end-to-end finfet cell architecture

摘要

A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor.

主权项

1. A data processing system adapted to process a computer implemented representation of a circuit design, comprising:
a data processor and memory coupled to the data processor, the memory storing instructions executable by the data processor, including instructions to match cells specified in a machine readable circuit description with cells in a cell library, the cell library including a plurality of cells having a base structure comprising:
a first block including a first set of semiconductor fins aligned in a first direction;a second block including a second set of semiconductor fins aligned in the first direction;an inter-block isolation structure in a third region having a first side adjacent to the first block and a second side adjacent to the second block, wherein semiconductor fins in the first set extend away from the inter-block isolation structure, have ends proximal to the first side of the inter-block isolation structure and have ends distal to the inter-block isolation structure, and wherein semiconductor fins in the second set extend away from the inter-block isolation structure, have ends proximal to the second side of the inter-block isolation structure and have ends distal to the inter-block isolation structure; cells in the plurality of cells including:
a patterned gate conductor layer on the base structure including a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins;a plurality of patterned conductor layers on the base structure, one or more conductive conductors in the plurality of patterned conductor layers being arranged to connect a semiconductor fin in the first set to a semiconductor fin in the second set, arranged to connect the first gate conductor to the second gate conductor, and arranged to connect a power conductor to at least one semiconductor fin in one of the first and second sets; anda plurality of interlayer connectors on the base structure that connect semiconductor fins, gate conductors, and conductors in the plurality of patterned conductor layers.