Delay line calibration circuit and method

摘要

In an approach for calibrating a delay line having a plurality of taps, a first clock signal is input to the delay line. A second clock signal is input to a reference circuit having a plurality of taps. In response to determining that output signals of selected taps of the delay line and reference circuit do not align, a next tap of the reference circuit is selected, to determine whether or not the output signals align. In response to determining that the output signals align, reference tap data indicative of the current reference tap is stored in association with a delay tap number of the current delay tap. A next tap of the delay line is selected to determine whether or not the output signals align.

主权项

1. A method of calibrating a delay line, comprising:
inputting a first clock signal to the delay line wherein the delay line has a plurality of taps; inputting a second clock signal to a reference circuit, wherein the second clock signal is different from the first clock signal and the reference circuit has a plurality of taps; selecting a first tap of the delay line as a current delay tap; selecting a first tap of the reference circuit as a current reference tap; determining whether or not output signals of the current delay tap and the current reference tap align; in response to determining that the output signals do not align:
repeating a selection of a next tap of the reference circuit as the current reference tap and a determination of whether or not the output signals align until the output signals align:storing reference tap data indicative of the current reference tap in association with a delay tap number of the current delay tap;selecting a next tap of the delay line as the current delay tap; andrepeating the determining whether or not the output signals align.