Programmable logic device structure using third dimensional memory

摘要

A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.

主权项

1. A re-writeable non-volatile Field Programmable Gate Array (FPGA), comprising:
a silicon substrate including a logic layer having active circuitry fabricated on the logic layer, the active circuitry including logic elements, and a logic configuration circuit electrically coupled with the logic elements; and a plurality of memory layers in contact with and vertically fabricated directly above the silicon substrate, vertically stacked upon one another, with each memory layer including a plurality of re-writeable non-volatile memory elements having exactly two-terminals, wherein the memory elements store data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across its two-terminals, the data can be reversibly written by applying a write voltage across its two-terminals, and the data is retained in the absence of electrical power, the memory elements are electrically coupled with the logic configuration circuit and are configured to store non-volatile routing data for a logic design, and the logic configuration circuit configured to access the routing data to configure one or more of the logic elements to implement the logic design.