发明名称 |
Array substrate and manufacturing method thereof |
摘要 |
A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the pixel region, wherein at least one of the pixel structures is formed by the following steps. A gate electrode, a gate insulating layer, and a source electrode and a drain electrode are formed. A patterned semiconductor layer including a first semiconductor pattern and a second semiconductor pattern is formed. The second semiconductor pattern covers a portion of the drain electrode. A first passivation layer is formed. The first passivation layer has a first opening exposing a portion of the second semiconductor pattern. A transparent conductive pattern is formed on the first passivation layer, and the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening. |
申请公布号 |
US8900900(B2) |
申请公布日期 |
2014.12.02 |
申请号 |
US201313772346 |
申请日期 |
2013.02.21 |
申请人 |
AU Optronics Corp. |
发明人 |
Chen Ming-Yao;Chen Pei-Ming |
分类号 |
H01L33/48;H01L33/08;H01L21/77 |
主分类号 |
H01L33/48 |
代理机构 |
|
代理人 |
Hsu Winston;Margo Scott |
主权项 |
1. A manufacturing method of an array substrate comprising:
providing a substrate having a pixel region and a peripheral region adjacent to the pixel region; forming a plurality of pixel structures in the pixel region, wherein steps of forming at least one of the pixel structures comprise:
forming a patterned first metal layer, a gate insulating layer, and a patterned second metal layer on the substrate, wherein the patterned first metal layer comprises a gate electrode, and the patterned second metal layer comprises a source electrode and a drain electrode ;forming a patterned semiconductor layer on the substrate, wherein the patterned semiconductor layer comprises a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern is substantially corresponding to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode, and the second semiconductor pattern covers a portion of the drain electrode;forming a first passivation layer on the substrate, wherein the first passivation layer has a first opening exposing a portion of the second semiconductor pattern; andforming a first patterned transparent conductive layer on the first passivation layer, wherein the first patterned transparent conductive layer comprises a transparent conductive pattern, the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening. |
地址 |
Science-Based Industrial Park, Hsin-Chu TW |