| 摘要 |
<p>A scan driver of the present invention comprises a level shifter which outputs a start signal, clock signals, and reset clock signals; and a shift register which is composed of stages for shifting and outputting a scan signal by corresponding to the start signal, the clock signals, and the reset clock signals. An N stage of the stages includes a pull-up transistor which outputs an N clock signal to the output terminal of the N stage by corresponding to the potential of a Q node; a pull-down transistor which outputs low-potential voltage to the output terminal of the N stage by corresponding to the potential of a QB node; a Q node charging and discharging part which charges and discharges the Q node; and a QB node charging and discharging part which charges and discharges the QB node. The QB node charging and discharging part maintains the QB node with the voltage between a logic high and a logic low after the low-potential voltage is outputted through the output terminal of the N stage.</p> |
