A TIME TO DIGITAL CONVERTER WITHOUT DELAY CELLS AND PHASE LOCKED LOOP INCLUDING THE SAME

摘要

The present invention relates to a time to digital converter without delay cell and a phase locked loop including the same. More particularly, the present invention relates to the time to digital converter without delay cell to improve phase difference detection performance, and a phase locked loop including the same. The time to digital converter without delay cell and a phase locked loop including the same according to an embodiment of the present invention includes flip flops including different setup times. According to an embodiment of the present invention, the flip flops include back-to-back invertors including a first invertor and a second invertor.