LEVEL SHIFTER FOR A LIQUID CRYSTAL DISPLAY

摘要

In described examples, a level shifter circuit (700) has a plurality of channels (706, 714, 722, 724) for providing signals to a capacitive load and has circuits (M3a, M3b, M3c, M3d) for sharing charge stored in the capacitive load between the channels (706, 714, 722, 724). A first pair of channel clock generating circuits (Mia, M2a, M1b, M2b) are coupled respectively to a first pair of channels (706, 722). A second pair of channel clock generating circuits (M1c, M2c, Mid, M2d) are coupled respectively to a second pair of channels (714, 724). A first pair of switches (M3a, M3b) couples the first pair of channels (706, 722) together, and a second pair of switches (M3c, M3d) couples the second pair of channels (714, 724) together, for sharing charge between the channels (706, 714, 722, 724). A single resistor (Res) is coupled in circuit with all of the channels (706, 714, 722, 724) for controlling a slope of charge sharing between the channels (706, 714, 722, 724).