发明名称 STRUCTURE AND METHOD FOR IMPLEMENTING POWER SAVINGS DURING ADDRESSING OF DRAM ARCHITECTURES
摘要 PROBLEM TO BE SOLVED: To provide a structure and method for implementing power savings during addressing of DRAM devices.SOLUTION: A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, where N corresponds to the number of independently accessible partitions of the array, and each access device in a given row is coupled to only one of the N word lines of the row. An address decoder in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, so that access devices within a selected row, but not within a partition to be accessed, are not activated.
申请公布号 JP2014222559(A) 申请公布日期 2014.11.27
申请号 JP20140156169 申请日期 2014.07.31
申请人 INTERNATIONAL BUSINESS MASCHINES CORPORATION 发明人 GERMANN PHILIP RAYMOND;BORKENHAGEN JOHN M;BECKER DARRYL J;BARTLEY GERALD KEITH;HOVIS WILLIAM PAUL
分类号 G11C11/401;G06F12/06;G11C11/407 主分类号 G11C11/401
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