发明名称 |
VALIDATION OF CACHE LOCKING USING INSTRUCTION FETCH AND EXECUTION |
摘要 |
A technique for locking a cache memory device (or portion thereof) which includes the following actions: (i) writing full traversal branching instructions in a cache way of a cache memory device; and (ii) subsequent to the writing step, locking the cache way. The locking action is performed by adjusting cache locking data to indicate that data in the cache way will not be overwritten during normal operations of the cache memory device. The writing action and the locking action are performed by a machine. |
申请公布号 |
US2014351517(A1) |
申请公布日期 |
2014.11.27 |
申请号 |
US201313899879 |
申请日期 |
2013.05.22 |
申请人 |
Garnett Pryor A.;International Business Machines Corporation |
发明人 |
Moharil Rahul S.;Sarath Lakshmi |
分类号 |
G06F12/14;G06F12/12;G06F12/08 |
主分类号 |
G06F12/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
Hillsboro OR US |