| 主权项 |
1. A digital signal up-converting apparatus, comprising:
a clock generating circuit, arranged to generate a reference clock signal; an adjusting circuit, coupled to the clock generating circuit, arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit, coupled to the adjusting circuit, for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit, coupled to the adjusting circuit and the baseband circuit, for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal. |
