发明名称 |
VERTICAL-CHANNEL TYPE JUNCTION SIC POWER FET AND METHOD OF MANUFACTURING SAME |
摘要 |
In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions. |
申请公布号 |
US2014346528(A1) |
申请公布日期 |
2014.11.27 |
申请号 |
US201414270469 |
申请日期 |
2014.05.06 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
HISADA Kenichi;ARAI Koichi |
分类号 |
H01L29/16;H01L29/808;H01L29/66 |
主分类号 |
H01L29/16 |
代理机构 |
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代理人 |
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主权项 |
1. A vertical-channel type junction SiC power FET, comprising:
(a) a SiC semiconductor substrate having a first main surface and a second main surface; (b) a drift region provided from a surface to an inside on the side of the first main surface of the SiC semiconductor substrate and having a first conductivity type; (c) a drain region provided in a surface region on the side of the second main surface of the SiC semiconductor substrate, more heavily doped than the drift region, and having the first conductivity type; (d) an active cell region extending from a surface to an inside of the drift region; and (e) a plurality of unit cell regions provided in the active cell region, wherein each of the unit cell regions, comprising: (e1) a source region provided in a surface region of the drift region, more heavily doped than the drift region, and having the first conductivity type; (e2) a floating region provided in the drift region so as to be below and contiguous to the source region and having a second conductivity type, that is, a conductivity type opposite to the first conductivity type; and (e3) gate regions provided in a surface region of the drift region so as to sandwich therewith the source region and the floating region at least from both sides thereof and having the second conductivity type. |
地址 |
Kanagawa JP |