Multi-processor with selectively interconnected memory units

摘要

A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.

主权项

1. A multi-processor, comprising:
a plurality of data processing units, each comprising an arithmetic logic unit; a plurality of memory units; and a bus system selectively interconnecting the plurality of data processing units and the plurality of memory units.