发明名称 RECONFIGURABLE CIRCUIT BLOCK SUPPORTING DIFFERENT INTERCONNECTION CONFIGURATIONS FOR RATE-CONVERSION CIRCUIT AND PROCESSING CIRCUIT AND RELATED METHOD THEREOF
摘要 A reconfigurable circuit block includes a rate-conversion circuit, a processing circuit, a first asynchronous interface circuit, and a second asynchronous interface circuit. The rate-conversion circuit converts a first input signal into a first output signal. The processing circuit processes a second input signal to generate a second output signal. The first asynchronous interface circuit outputs a third output signal asynchronous with the first output signal. The second asynchronous interface circuit outputs a fourth output signal asynchronous with the second output signal. The controllable interconnection circuit transmits the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmits the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration.
申请公布号 US2014347094(A1) 申请公布日期 2014.11.27
申请号 US201414280651 申请日期 2014.05.18
申请人 MEDIATEK INC. 发明人 Hsieh Ming-Yu;Muhammad Khurram;Chang Pou-Chi
分类号 H03K19/0175 主分类号 H03K19/0175
代理机构 代理人
主权项 1. A reconfigurable circuit block, comprising: a rate-conversion circuit, configured to convert a first input signal with a first data rate into a first output signal with a second data rate that is different from the first data rate; a processing circuit, configured to perform a predetermined signal processing operation upon a second input signal to generate a second output signal; a first asynchronous interface circuit, configured to receive the first output signal, and output a third output signal asynchronous with the first output signal; a second asynchronous interface circuit, configured to receive the second output signal, and output a fourth output signal asynchronous with the second output signal; and a controllable interconnection circuit, coupled to the rate-conversion circuit, the processing circuit, the first asynchronous interface circuit, and the second asynchronous interface circuit, wherein the controllable interconnection circuit is configured to transmit the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmit the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration.
地址 Hsin-Chu TW