INTEGRATED BONDLINE SPACERS FOR WAFER LEVEL PACKAGED CIRCUIT DEVICES

摘要

A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

主权项

1. A wafer level packaged circuit device, comprising:
a device wafer bonded to a cap wafer; and an integrated bond gap control structure (BGCS) disposed between the device wafer and the cap wafer, the integrated BGCS comprising one or more material layers used in the formation of at least one of the cap wafer and the device wafer, and left remaining in a region of a substrate of at least one of the cap wafer and the device wafer.