发明名称 データ処理装置、及び、データ処理方法
摘要 <p>When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i + 1)-th bit from a most significant bit of code bits of 4 x 2 bits and a (#i + 1)-th bit from a most significant bit of symbol bits of 4 x 2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for an LDPC codes having coding rates of 7/15, b0 is allocated to y0, b1 is allocated to y2, b2 is allocated to y6, b3 is allocated to y3, b4 is allocated to y4, b5 is allocated to y1, b6 is allocated to y5, and b7 is allocated to y7.</p>
申请公布号 JP5630283(B2) 申请公布日期 2014.11.26
申请号 JP20110008753 申请日期 2011.01.19
申请人 发明人
分类号 H03M13/19;H04L27/00 主分类号 H03M13/19
代理机构 代理人
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