Programmable frequency divider module with duty cycle close to fifty percent

摘要

A programmable frequency divider module (10) is based on a programmable re-load counter (1) and a digital combination (11) comprising an N-bit adder. In a preferred implementation, a down-count from a division ratio value (R) down to one-value is repeated, and a down-count signal is added to an offset value itself determined as a function of the division ratio value. The adder carry generates a derived clock signal having a frequency equal to that of an initial clock signal divided by the division ratio value. Such frequency divider module produces the derived clock signal with low noise and duty cycle close to 50%. It is well adapted in particular for clocking analog-to-digital converters, digital-to-analog converters and phase-locked loop devices.