| 摘要 |
A signal processing apparatus 10 comprises: a first computing unit 12; a second computing unit 14; a data memory 22; and a register file 16 which comprises a first register bank 18 and a second register bank 20. The apparatus is configured to alternate between a first and a second phase of operation, where: in the first phase, it is configured to read results data from the second register bank into the data memory and to write computation data from the data memory into the second register bank while the computing units perform a processing operation on data read from the first register bank (cycles 0 to 7 of Figure 4); and in the second phase, it is configured to read results data from the first register bank into the data memory and to write computation data from the data memory into the first register bank while the computing units perform a processing operation on data read from the second register bank (cycles 8 to 15 (not shown) of Figure 4). The dual bank register file 16 effectively provides a ping pong register, where banks are switched or swapped between operation phases. |
